Semiconductor-on-diamond devices and associated methods

ABSTRACT

Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (AlP), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation.

PRIORITY DATA

This application is a continuation of U.S. patent application Ser. No.12/360,326, filed on Jan. 27, 2009, which is a divisional of U.S. patentapplication Ser. No. 11/440,793, filed on May 22, 2006, each of which isincorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to methods of making substrateshaving a semiconductor layer disposed on a diamond substrate, as well asassociated devices. Accordingly, the present invention involves thechemical and material science fields.

BACKGROUND OF THE INVENTION

As computers and other electronic devices become smaller and faster, thedemands placed on semiconductor devices utilized therein increasegeometrically. Ultra-large-scale integration (ULSI) is a technology thatplaces at least 1 million circuit elements on a single semiconductorchip. In addition to the tremendous density issues that already exist,with the current movement toward size reduction, ULSI is becoming evenmore delicate, both in size and materials than ever before. As currenttechnology moves beyond ULSI, several barriers emerge that may beinsurmountable with current wafer and substrate materials.

One barrier arises due to the accumulation of heat that may not beeffectively channeled out of the crystal lattice of Group IVsemiconductors. Semiconductors tend to have thermal conductivities thatare a fraction of copper metal. Hence, semiconductor devices are oftencooled with copper heat spreaders. However, as the power requirementsfuture generations of semiconductor devices increase, copper heatspreaders will become reservoirs for heat accumulation.

Another barrier arises due to the accumulation of charge carriers, i.e.electrons and holes, which are intrinsic to quantum fluctuation.Accumulation of the carriers creates noise, and tends to obscureelectrical signals within the semiconductor device. This problem iscompounded as the temperature of the device increases. Much of thecarrier accumulation may be due to the intrinsically low bonding energyand the directional anisotropy of typical semiconductor crystallattices.

Yet another barrier may be a further result of current semiconductormaterials. These semiconductors tend to have a high leaking current anda low break down voltage. As the size of semiconductor transistors andother circuit elements decrease, coupled with the growing need toincrease power and frequency, current leak and break down voltage alsobecome critical.

As power and frequency requirements increase and the size ofsemiconductor components decreases, the search for materials toalleviate these problems becomes crucial to the progress of thesemiconductor industry. One material that may be suitable for the nextgeneration of semiconductor devices is diamond. The physical propertiesof diamond, such as its high thermal conductivity, low intrinsic carrierconcentration, and high band gap make it a desirable material for use inmany high-powered electronic devices.

The semiconductor industry has recently expanded efforts in producingsemiconductor-on-insulator (SOI) devices. These devices allow forelectrical insulation between an underlying substrate and any number ofuseful semiconductor devices. Typically, these SOI devices utilizeinsulating layers with poor thermal conductivity, high degree of thermalexpansion mismatch, and/or difficulties in epitaxial growth of siliconor other semiconductor materials. In light of some of thesedifficulties, various efforts have explored using diamond as theinsulating layer with some success. However, such devices continue tobenefit from further improvement such as decreasing manufacturing costs,improving performance, and the like.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides semiconductor-on-diamond(SOD) substrates and methods for making such substrates. In one aspect,a method of making an SOD substrate is provided. Such a method mayinclude depositing a base layer onto a lattice-orienting silicon (Si)substrate such that the base layer lattice is substantially oriented bythe Si substrate. The base layer may include numerous materials,including, without limitation, aluminum phosphide (AlP), boron arsenide(BAs), gallium nitride (GaN), indium nitride (InN), and combinationsthereof. The method may further include depositing a semiconductor layeronto the base layer such that the semiconductor layer lattice issubstantially oriented with respect to the base layer lattice, anddisposing a layer of diamond onto the semiconductor layer. The methodmay further include removing the lattice-orienting Si substrate and thebase layer from the semiconductor layer. In one aspect, the Si substratemay be of a single crystal orientation.

Various semiconductor layers may be deposited onto the base layer,depending on the intended utility of the SOD substrate. For example, inone aspect the semiconductor layer may be a layer of gallium nitride(GaN) and the base layer may be InN. The GaN may be deposited on the InNlayer by any means known to one of ordinary skill in the art. In onespecific aspect, however, the GaN layer may be deposited onto the layerof InN by gradually transitioning the layer of InN into the layer ofGaN. For example, gradually transitioning the layer of InN into thelayer of GaN may include fixing the concentration of N being depositedand varying the deposited concentration of Ga and of In such that aratio of Ga:In gradually transitions from about 0:1 to about 1:0.

In another aspect, the semiconductor layer may be a layer of AlN and thebase layer may be InN. The AlN layer may be deposited onto the InN layerby any means known to one of ordinary skill in the art. In one specificaspect, however, the AlN may be deposited onto the layer of InN bygradually transitioning the layer of InN into the layer of AlN. In oneaspect, for example, gradually transitioning the layer of InN into thelayer of AlN may include fixing the concentration of N being depositedand varying the deposited concentration of In and of Al such that aratio of In:Al gradually transitions from about 0:1 to about 1:0.

In yet another aspect, the semiconductor layer may include both GaN andAlN and the base layer may be InN. As has been described, the depositionof GaN and AlN may be by any means known to one of ordinary skill in theart. As such, in one aspect depositing the semiconductor layer mayfurther include depositing a layer of GaN onto the layer of InN suchthat the GaN layer lattice is substantially oriented with respect to theInN layer lattice, and depositing a layer of AlN onto the layer of GaNsuch that the AlN layer lattice is substantially oriented with respectto the GaN layer lattice. Though various methods of substantiallyorienting a lattice with respect to another are contemplated, one methodmay be by gradual transition from one layer to another. For example,depositing the AlN and GaN layers onto the InN layer may includegradually transitioning the layer of InN into the layer of GaN andsubsequently gradually transitioning the layer of GaN into the layer ofAlN. Gradually transitioning the layer of GaN into the layer of AlN mayfurther include fixing the concentration of N being deposited andvarying the deposited concentration of Ga and of Al such that a ratio ofGa:Al gradually transitions from about 0:1 to about 1:0. The method mayfurther include removing the GaN layer from the AlN layer. Additionally,any of the semiconductor layers formed according to aspects of thepresent invention may have a single crystal orientation as a result offormation by the deposition methods disclosed herein.

Various steps can further be taken to improve the lattice matchingbetween the Si to substrate and the base layer. For example, in oneaspect a layer of SiC may be deposited onto the lattice-orienting Sisubstrate such that the SiC layer lattice is substantially oriented bythe Si substrate and the base layer may be deposited onto SiC layer suchthat the base layer lattice is substantially oriented with respect tothe SiC layer lattice.

The lattice of the semiconductor layer may be formed in variousorientations by depositing the base layer onto a specific face of the Sisubstrate. For example, in one aspect the base layer may be depositedonto a (100) face of the lattice-orienting Si substrate such that thebase layer is deposited as a cubic base layer. Subsequent deposition ofthe semiconductor layer onto the cubic base layer may form apredominantly cubic semiconductor layer due to the orientation of thebase layer. For example, if the base layer is InN, then cubic InN may bedeposited on the Si substrate. Subsequent deposition of thesemiconductor layers may result in a cubic semiconductor layer such ascubic GaN.

Numerous methods of disposing a layer of diamond onto the semiconductorlayer are contemplated. In one aspect, the layer of diamond may beformed on the semiconductor layer. In another aspect, the layer ofdiamond may be bonded to the semiconductor layer. In such cases, thediamond layer may be formed separately from the semiconductor layer andsubsequently bonded thereto. Furthermore, the diamond layer may becoupled to a support substrate.

Aspects of the present invention may also include SOD devices. Forexample, in one aspect an SOD device may include a layer of diamond anda single crystal semiconductor layer disposed onto to the diamond layer,where the single crystal semiconductor layer may include AlN, GaN, andcombinations thereof. The single crystal semiconductor layer may alsoinclude cubic forms of the semiconductor, including cubic AlN, cubicGaN, and combinations thereof.

Numerous devices are contemplated that may include the SOD devicesaccording to aspects of the present invention. For example, in oneaspect the SOD device may be an LED. In another aspect, the SOD devicemay be an acoustic filter such as a SAW filter. In yet another aspect,the SOD device may be a semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sequential depiction of a method of making an SOD device inaccordance with one embodiment of the present invention.

FIG. 2 is a sequential depiction of a method of making an SOD device inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION

Before the present invention is disclosed and described, it is to beunderstood that this invention is not limited to the particularstructures, process steps, or materials disclosed herein, but isextended to equivalents thereof as would be recognized by thoseordinarily skilled in the relevant arts. It should also be understoodthat terminology employed herein is used for the purpose of describingparticular embodiments only and is not intended to be limiting.

It must be noted that, as used in this specification and the appendedclaims, the singular forms “a,” and, “the” include plural referentsunless the context clearly dictates otherwise. Thus, for example,reference to “an intermediate layer” includes one or more of suchlayers, reference to “a carbon source” includes reference to one or moreof such carbon sources, and reference to “a CVD technique” includesreference to one or more of such CVD techniques.

Definitions

In describing and claiming the present invention, the followingterminology will be used in accordance with the definitions set forthbelow.

As used herein, “substrate” refers to a support surface to which variousmaterials can be joined in forming a silicon-on-diamond (SOD) device.The substrate may be any shape, thickness, or material, required inorder to achieve a specific result, and includes but is not limited tometals, alloys, ceramics, and mixtures thereof. Further, in someaspects, the substrate may be an existing semiconductor device or wafer,or may be a material which is capable of being joined to a suitabledevice.

As used herein, “nucleation enhancer” refers to a material, whichincreases the quality of a diamond layer formed from a plurality ofdiamond nuclei using a CVD process. In one aspect, the nucleationenhancer may increase the quality of a diamond layer by reducingmovement or immobilizing diamond nuclei. Examples of nucleationenhancers include without limitation, metals, and various metalliccompounds, as well as carbides and carbide forming materials.

As used herein with respect to a nucleation enhancer layer and anintermediate layer, “thin” refers to the thickness or depth of the layerbeing sufficiently small so as to not substantially interfere with thetransfer of the intended configuration from the interface surfaceconfiguration to the device surface. In one aspect, the thickness of thenucleation enhancer may be less than about 0.1 micrometers. In anotheraspect, the thickness may be less than 10 nanometers. In another aspect,the thickness may be less than about 5 nanometers.

As used herein, “working surface” refers to the surface of a diamondlayer which contacts a semiconductor, an intermediate layer, a wurtziticboron nitride layer, or other electronic device.

As used herein, “diamond layer” refers to any structure, regardless ofshape, which contains diamond-containing materials which can beincorporated into a SOD device. Thus, for example, a diamond filmpartially or entirely covering a surface is included within the meaningof these terms. Additionally, a layer of a material, such as metals,acrylics, or composites, having diamond particles disbursed therein isincluded in these terms.

As used herein, “grain boundaries” are boundaries in a crystallinelattice formed where adjacent seed crystals have grown together. Anexample includes polycrystalline diamond, where numerous seed crystalshaving grains of different orientations have grown together to form aheteroepitaxial layer.

As used herein, “crystal dislocations” or “dislocations” can be usedinterchangeably, and refer to any variation from essentially perfectorder and/or symmetry in a crystalline lattice.

As used herein, “single crystal” refers to a crystalline material havinga crystal lattice that is substantially free of crystal dislocationsand/or grain boundaries.

As used herein, “vapor deposited” refers to materials which are formedusing vapor deposition techniques. “Vapor deposition” refers to aprocess of depositing materials on a substrate through the vapor phase.Vapor deposition processes can include any process such as, but notlimited to, chemical vapor deposition (CVD) and physical vapordeposition (PVD). A wide variety of variations of each vapor depositionmethod can be performed by those skilled in the art. Examples of vapordeposition methods include hot filament CVD, rf-CVD, laser CVD (LCVD),laser ablation, conformal diamond coating processes, metal-organic CVD(MOCVD), sputtering, thermal evaporation PVD, ionized metal PVD (IMPVD),electron beam PVD (EBPVD), reactive PVD, and the like. As used herein,“chemical vapor deposition,” or “CVD” refers to any method of chemicallydepositing diamond or other particles in a vapor form upon a surface.Various CVD techniques are well known in the art.

Methods for incorporating diamond or diamond-like materials into an SODdevice can include known processes such as chemical vapor deposition(CVD) and physical vapor deposition (PVD). Various CVD techniques havebeen used in connection with depositing diamond or diamond-likematerials onto a substrate. Typical CVD techniques use gas reactants todeposit the diamond or diamond-like material in a layer, or film. Thesegases generally include a small amount (i.e. less than about 5%) of acarbonaceous material, such as methane, diluted in hydrogen. A varietyof specific CVD processes, including equipment and conditions, are wellknown to those skilled in the art.

As used herein, the term “substantially” refers to the complete ornearly complete extent or degree of an action, characteristic, property,state, structure, item, or result. For example, an object that is“substantially” enclosed would mean that the object is either completelyenclosed or nearly completely enclosed. The exact allowable degree ofdeviation from absolute completeness may in some cases depend on thespecific context. However, generally speaking the nearness of completionwill be so as to have the same overall result as if absolute and totalcompletion were obtained. The use of “substantially” is equallyapplicable when used in a negative connotation to refer to the completeor near complete lack of an action, characteristic, property, state,structure, item, or result. For example, a composition that is“substantially free of” particles would either completely lackparticles, or so nearly completely lack particles that the effect wouldbe the same as if it completely lacked particles. In other words, acomposition that is “substantially free of” an ingredient or element maystill actually contain such item as long as there is no measurableeffect thereof.

As used herein, the term “about” is used to provide flexibility to anumerical range endpoint by providing that a given value may be “alittle above” or “a little below” the endpoint.

As used herein, a plurality of items, structural elements, compositionalelements, and/or materials may be presented in a common list forconvenience. However, these lists should be construed as though eachmember of the list is individually identified as a separate and uniquemember. Thus, no individual member of such list should be construed as ade facto equivalent of any other member of the same list solely based ontheir presentation in a common group without indications to thecontrary.

Concentrations, amounts, and other numerical data may be expressed orpresented herein in a range format. It is to be understood that such arange format is used merely for convenience and brevity and thus shouldbe interpreted flexibly to include not only the numerical valuesexplicitly recited as the limits of the range, but also to include allthe individual numerical values or sub-ranges encompassed within thatrange as if each numerical value and sub-range is explicitly recited. Asan illustration, a numerical range of “about 1 to about 5” should beinterpreted to include not only the explicitly recited values of about 1to about 5, but also include individual values and sub-ranges within theindicated range. Thus, included in this numerical range are individualvalues such as 2, 3, and 4 and sub-ranges such as from 1-3, from 2-4,and from 3-5, etc., as well as 1, 2, 3, 4, and 5, individually.

This same principle applies to ranges reciting only one numerical valueas a minimum or a maximum. Furthermore, such an interpretation shouldapply regardless of the breadth of the range or the characteristicsbeing described.

The Invention

The present invention provides methods for making substantially singlecrystal semiconductor layers disposed on diamond substrates, and devicesincorporating the same. The consecutive deposition of semiconductorlayers having substantially different lattice sizes generally creates alattice mismatch between the resulting layers. Significant latticemismatch will cause high interface stress and high dislocation densityin the resulting semiconductor device. The inventor has discovered thatlayers of materials deposited in particular orders can be used togenerate increased levels of lattice matching, resulting in theformation of substantially single crystal semiconductor layers with verylow interface stress and very low dislocation densities. This inventionadditionally entertains the use of a gradational composition thattransitions between semiconductor lattices of different sizes in orderto construct various single crystal semiconductor layers. Variousmethods of creating a gradational composition can be utilized in thepresent invention, including the amorphous mixing of atoms and thereplacement of atoms in a fixed crystal lattice. A discussion ofamorphous mixing to create a gradational composition can be found inApplicant's copending U.S. patent application Ser. No. 10/837,242 filedon Apr. 30, 2004, which is hereby incorporated by reference.

For example, in one aspect of the present invention a method of making asemiconductor-on-diamond (SOD) substrate is provided that includesdepositing a base layer onto a lattice-orienting Si substrate such thatthe base layer lattice is substantially oriented by the Si substrate,depositing a semiconductor layer onto the base layer such that thesemiconductor layer lattice is substantially oriented with respect tothe base layer lattice, and disposing a layer of diamond onto thesemiconductor layer. The lattice-orienting Si substrate and the baselayer may be removed from the semiconductor layer to provide a singlecrystal semiconductor layer deposited on a diamond layer.

Various materials are contemplated that may be included in the baselayer, and as such, the base layer should not be limited to theexemplary materials described herein. In one aspect, for example, thebase layer materials may be selected to approximate or otherwisecorrespond to the interatomic distances of the Si substrate. Examples ofsuch materials may include, without limitation, AlP, BAs, GaN, InN, andcombinations thereof

In one specific aspect, the base layer may include AlP. In anotherspecific aspect, the base layer may include BAs. In yet another specificaspect, the base layer may include GaN. In a further specific aspect,the base layer may include InN. It should be noted that much of thefollowing discussion describes InN as the base layer material, and thatthis description is merely for convenience in describing aspects of thepresent invention. As such, no limitation is thereby intended.

By minimizing the lattice mismatch between layers, the single crystalnature of the Si substrate can be carried thought the various layers ofthe SOD device to form a single crystal semiconductor layer thereon. Anideal lattice match between layers will have a similar crystal structureand a similar atomic size with the diamond layer. Such similarities willthus improve the lattice matching, i.e. the one-to-one correspondence ofatoms, across the boundary between the different materials. The higherthe degree of lattice matching, the lower the likelihood that crystaldislocations and other defects will be propagated across thediamond-buffer layer boundary. Thus the degree of lattice matching willaffect the performance and reliability of the SOD device. In addition,lattice matching also reduces stress across the boundary due todifferential thermal expansion of the layers.

Various procedural steps may be taken to increase the likelihood offorming single crystal layers. For example, by selecting materials ofadjoining layers that have a lattice mismatch (see Table 1) that is lessthan about 5%, the likelihood of grain boundaries and latticedislocations is significantly decreased. It may be beneficial to keepthe lattice mismatch below about 5% in order to minimize the dislocationdensity in an epitaxial layer. For those adjoining layers having alattice mismatch greater than about 5%, compositional grading betweenlayers may also decrease the likelihood of grain boundaries and latticedislocations forming between the layers. Accordingly, during thedeposition, if at least half of the compositional elements in thelattice can be kept the same, the composition can be graded by thecompositional change as discussed herein. Compositional grading may beaccomplished by any means known and as described herein.

TABLE 1 Lattice Mismatch Between Elements CC BN SiC AlN GaN InN SiSi CC0 −2 −26 −32 −35 −50 −53 BN 2 0 −24 −29 −32 −47 −50 SiC 26 24 0 −5 −7−19 −21 AlN 32 29 5 0 −2 −14 −16 GaN 35 32 7 2 0 −11 −13 InN 50 47 19 1411 0 −2 SiSi 53 50 21 16 13 2 0

Si substrates are useful materials for the construction of the singlecrystal semiconductor layers of the present invention. Si can readily beproduced as a single crystal wafer or substrate. This single crystalnature assists in orienting subsequently deposited semiconductor layersas substantially single crystal structures.

As shown in FIG. 1, InN 12 may be deposited on a lattice-orienting Sisubstrate 10. Various methods of depositing InN onto the Si substrateare contemplated, all of which are considered to be within the scope ofthe present invention. In one aspect, InN may be deposited on the Sisubstrate using MOCVD techniques. As is shown in Table 1, the latticemismatch between SiSi and InN is approximately 2%. Such close latticemismatching may allow InN to be deposited onto the Si substrate as asubstantially single crystal. The lattice mismatch may be furtherimproved during the deposition, however, through compositionally gradingbetween the layers. In other words, the Si substrate can be graduallygraded into InN to further reduce the level of lattice mismatchingbetween the two layers. Such grading can be accomplished by doping thesurface of the Si substrate with In atoms. Doping methods are known tothose of ordinary skill in the art. MOCVD deposition can then beperformed on the doped surface with silicon and gases containing indiumand nitrogen. Suitable silicon sources may include, without limitation,silane, SiH₄, etc. Examples of indium and nitrogen sources may include,without limitation, InH₃ and NH₃, respectively. Accordingly, the gradingmay occur during deposition over time by decreasing the concentration ofthe Si source, increasing the concentration of the In source, andgradually introducing and increasing nitrogen source. Such a processprovides a gradual transition from Si to InN that has minimal latticedislocations and grain boundaries. A similar process may be performedfor other base layer materials. For example, Si may be doped with Aland/or P followed by MOCVD deposition of Si, Al, and P to form a gradedSi to ALP base layer.

Various methods may also be utilized to increase the epitaxialdeposition between materials. In one aspect, the deposition surface, orsurface receiving the deposition, may be roughened to increase theuniformity of the crystal lattice orientation of the deposited layer.For example, the surface of the Si substrate can be roughened to formpits or tips. If the tips or pits are close enough, dislocations willnot be trapped within the lattice as they grow, but will meet early ingrowth and thus merge into a continuous lattice. As an example, in oneaspect pits or tips may have an average spacing of less than about 5microns. In another aspect, pits or tips may have an average spacing ofless than about 1 micron. In yet another aspect, pits or tips may havean average spacing of less than about 0.5 microns. In a further aspect,pits or tips may have an average spacing of less than about 0.1 micron.Such roughing can be accomplished by any means known to one of ordinaryskill in the art, such as, for example, sand blasting, sanding, chemicaletching, ultrasound etching, electrical etching, etc. Additionally, suchroughening may be utilized to improve epitaxy between any adjacentlayers, such as between the Si substrate and the base layer, between thebase layer and the semiconductor layer, between multiple semiconductorlayers, etc.

Returning to FIG. 1, a semiconductor layer 14 can be deposited on theInN layer 12. The semiconductor layers of the present invention maycomprise any material that is suitable for forming electronic devices,semiconductor devices, or the like. Most semiconductors are based onsilicon, gallium, indium, and germanium. However, suitable materials forthe semiconductor layer can include, without limitation, silicon,silicon carbide, gallium arsenide, gallium nitride, germanium, zincsulfide, gallium phosphide, gallium antimonide, gallium indium arsenidephosphide, aluminum gallium arsenide, gallium nitride, boron nitride,aluminum nitride, indium arsenide, indium phosphide, indium antimonide,indium nitride, and composites thereof. In one embodiment, thesemiconductor layer can comprise silicon, silicon carbide, galliumarsenide, gallium nitride, aluminum nitride, indium nitride, indiumgallium nitride, aluminum gallium nitride, or composites of thesematerials. In some additional embodiments, non-silicon based devices canbe formed such as those based on gallium arsenide, gallium nitride,germanium, boron nitride, aluminum nitride, indium-based materials, andcomposites thereof. In another embodiment, the semiconductor layer cancomprise gallium nitride, indium gallium nitride, indium nitride, andcombinations thereof. Other semiconductor materials which can be usedinclude Al₂O₃, BeO, W, Mo, c-Y₂O₃, c-(Y_(0.9)La_(0.1))₂O₃, c-Al₂₃O₂₇N₅,c-MgAl₂O₄, t-MgF₂, graphite, and mixtures thereof. It should beunderstood that the semiconductor layer may include any semiconductormaterial known, and should not be limited to those materials describedherein. Additionally, semiconductor materials may be of any structuralconfiguration known, for example, without limitation, cubic (zincblendeor sphalerite), wurtzitic, rhombohedral, graphitic, turbostratic,pyrolytic, hexagonal, amorphous, or combinations thereof.

In one aspect, the semiconductor layer can be AlN, GaN, and combinationsthereof. Noting from Table 1 that the lattice mismatch between InN andeither of AlN or GaN is greater than 5%, grading between the layersshould be utilized in order to maintain the substantially single crystalnature of the InN layer into the semiconductor layer. The semiconductorlayer may be deposited by any method known to one of ordinary skill inthe art. Various known methods of vapor deposition can be utilized todeposit such layers and that allow deposition to occur in a gradedmanner.

In one aspect of the present invention, the semiconductor layer may beGaN. GaN semiconductor layers may be useful in constructing LEDs andother SOD devices. Gradually transitioning the InN layer into the GaNlayer may occur by fixing the concentration of the N being deposited andvarying the deposited concentration of Ga and of In such that a ratio ofGa:In gradually transitions from about 0:1 to about 1:0. In other words,the sources of Ga and In are varied such that as the In concentration isdecreased, the Ga concentration is increased. The gradual transitionfunctions to greatly reduce the lattice mismatch observed whendepositing GaN directly on InN.

In another aspect, the semiconductor layer may be a layer of AlN. TheAlN layer may be deposited onto the InN layer by any means known to oneof ordinary skill in the art. In order to minimize the lattice mismatchbetween InN and AlN, however, in one aspect the AlN may be depositedonto the layer of InN by gradually transitioning the layer of InN intothe layer of AlN. In one aspect, for example, gradually transitioningthe layer of InN into the layer of AlN may include fixing theconcentration of N being deposited and varying the depositedconcentration of In and of Al such that a ratio of In:Al graduallytransitions from about 0:1 to about 1:0. Such a gradual transition maygreatly reduce the lattice mismatch observed when depositing AlN on InNdirectly. Surface processing may be performed between any of thedeposition steps described in order to provide a smooth surface forsubsequent deposition. Such processing may be accomplished by any meansknown, such as by chemical etching, polishing, buffing, grinding, etc.

As is shown in FIG. 1, following the deposition of the semiconductorlayer 14 onto the InN layer 12, a layer of diamond 16 may be disposedonto the semiconductor layer 14. The diamond layer 16 may providevarious benefits to the SOD substrate, including temperature regulation,acoustic propagation, etc. Any form of diamond layer known may beutilized in the various aspects of the present invention, includingsingle crystal diamond, polycrystalline diamond, diamond-like carbon,amorphous diamond, etc. The diamond layer may be formed directly on thesemiconductor layer, or it may be formed separately from thesemiconductor layer and subsequently coupled thereto.

In those aspects wherein the diamond layer is formed directly on thesemiconductor layer, such formation may occur by any means know to oneof ordinary skill in the art. The most common vapor depositiontechniques include CVD and PVD, although any similar method can be usedif similar properties and results are obtained. In one aspect, CVDtechniques such as hot filament, microwave plasma, oxyacetylene flame,rf-CVD, laser CVD (LCVD), metal-organic CVD (MOCVD), laser ablation,conformal diamond coating processes, and direct current arc techniquesmay be utilized. Typical CVD techniques use gas reactants to deposit thediamond or diamond-like material in a layer, or film. These gasesgenerally include a small amount (i.e. less than about 5%) of acarbonaceous material, such as methane, diluted in hydrogen. A varietyof specific CVD processes, including equipment and conditions, are wellknown to those skilled in the art. Additionally, many of the describedtechniques may be utilized in the deposition of base and/orsemiconductor layers.

An optional nucleation enhancing layer can be formed on the growthsurface of the semiconductor layer in order to improve the quality anddeposition time of the diamond layer. Specifically, the diamond layercan be formed by depositing applicable nuclei, such as diamond nuclei,on the interface surface of the semiconductor layer and then growing thenuclei into a film or layer using a vapor deposition technique. In oneaspect of the present invention, a thin nucleation enhancer layer can becoated upon the semiconductor layer to enhance the growth of the diamondlayer. Diamond nuclei are then placed upon the nucleation enhancerlayer, and the growth of the diamond layer proceeds via CVD as describedherein.

A variety of suitable materials will be recognized by those in skilledin the art which can serve as a nucleation enhancer. In one aspect ofthe present invention, the nucleation enhancer may be a materialselected from the group consisting of metals, metal alloys, metalcompounds, carbides, carbide formers, and mixtures thereof. Examples ofcarbide forming materials include without limitation, tungsten (W),tantalum (Ta), titanium (Ti), zirconium (Zr), chromium (Cr), molybdenum(Mo), silicon (Si), and manganese (Mn). Additionally, examples ofcarbides include tungsten carbide (WC), silicon carbide (SiC), titaniumcarbide (TiC), zirconium carbide (ZrC), and mixtures thereof amongothers.

The nucleation enhancer layer, when used, is a layer which is thinenough that it does not to adversely affect the transfer of the intendedconfiguration from the interface surface to the device surface. In oneaspect, the thickness of the nucleation enhancer layer may be less thanabout 0.1 micrometers. In another aspect, the thickness may be less thanabout 10 nanometers. In yet another aspect, the thickness of thenucleation enhancer layer is less than about 5 nanometers. In a furtheraspect of the invention, the thickness of the nucleation enhancer layeris less than about 3 nanometers.

Various methods may be employed to increase the quality of the diamondin the nucleation surface of the diamond layer which is created by vapordeposition techniques. For example, diamond particle quality can beincreased by reducing the methane flow rate, and increasing the totalgas pressure during the early phase of diamond deposition. Suchmeasures, decrease the decomposition rate of carbon, and increase theconcentration of hydrogen atoms. Thus a significantly higher percentageof the carbon will be deposited in a sp³ bonding configuration, and thequality of the diamond nuclei formed is increased. Additionally, thenucleation rate of diamond particles deposited on the growth surface ofthe semiconductor layer or the nucleation enhancer layer may beincreased in order to reduce the amount of interstitial space betweendiamond particles. Examples of ways to increase nucleation ratesinclude, but are not limited to: applying a negative bias in anappropriate amount, often about 100 volts, to the growth surface;polishing the growth surface with a fine diamond paste or powder, whichmay partially remain on the growth surface; and controlling thecomposition of the growth surface such as by ion implantation of C, Si,Cr, Mn, Ti, V, Zr, W, Mo, Ta, and the like by PVD or PECVD. PVDprocesses are typically at lower temperatures than CVD processes and insome cases can be below about 200° C. such as about 150° C. Othermethods of increasing diamond nucleation will be readily apparent tothose skilled in the art.

In one aspect of the present invention, the diamond layer may be aconformal diamond layer. Conformal diamond coating processes can providea number of advantages over conventional diamond film processes.Conformal diamond coating can be performed on a wide variety ofsubstrates, including non-planar substrates. A growth surface can bepretreated under diamond growth conditions in the absence of a bias toform a carbon film. The diamond growth conditions can be conditionswhich are conventional CVD deposition conditions for diamond without anapplied bias. As a result, a thin carbon film can be formed which istypically less than about 100 angstroms. The pretreatment step can beperformed at almost any growth temperature such as from about 200° C. toabout 900° C., although lower temperatures below about 500° C. may bepreferred. Without being bound to any particular theory, the thin carbonfilm appears to form within a short time, e.g., less than one hour, andis a hydrogen terminated amorphous carbon. Further, the diamond filmtypically begins growth substantially over the entire substrate. Inaddition, a continuous film, e.g. substantially no grain boundaries, candevelop within about 80 nm of growth.

As has been described, in one more detailed aspect of the presentinvention, the growth surface can be etched with micro-scratches toenhance nucleation. One method of introducing such micro-scratches is toimmerse the semiconductor layer in an acetone bath containing suspendedmicron-size diamond particles. Ultrasonic energy can then be applied tothe semiconductor layer and/or the fluid. Upon removal from theultrasonic bath, a portion of the micron-sized diamonds remains on thesurface as diamond growth seeds.

In those aspect wherein the diamond layer is formed separately from thesemiconductor layer, such formation may also occur by any means know. Inaddition to various chemical and physical deposition techniques (e.g.CVD, MOCVD, PVD, etc.), various high-pressure high-temperature processesmay be utilized to form the diamond layer. One example of a high qualitydiamond layer formed under such conditions may be found in U.S. patentapplication Ser. No. 11/200,647, filed on Aug. 9, 2005, which isincorporated herein by reference in its entirety.

Diamond layers formed separately from the semiconductor layer may becoupled thereto by any means known. In one aspect, for example, thediamond layer may be coupled to the semiconductor layer using anadhesive or bonding material. Though various methods of bonding thelayers of the present invention together are contemplated, such bondingcan occur by using an ultra thin layer of bonding material. Prior tobonding, corresponding adjoining surfaces may be polished or prepared tohave a comparable surface roughness. The surface roughness will dependon the intended final device. Subsequently, an ultra thin layer ofbonding material may be produced by forming a layer of bonding materialon either of the surfaces to be joined and then pressing the twosurfaces together in order to reduce the bonding layer thickness to lessthan about 1 micron and preferably less than about 10 nanometers (i.e.only a few molecules thick). The bonding material may comprise anorganic binder such as an epoxy or may be a reactive metal such as Ti,Si, Zr, Cr, Mo, W, Mn, or mixtures thereof. In the case of a reactivemetal, the metal may be sputtered on either surface and then pressedagainst the other surface under heat and vacuum conditions. At theseultra thin thicknesses, the bonding material is more stable at highertemperatures. For example, typical epoxy binders will fail attemperatures above about 200° C.; however at ultra thin thicknesses theepoxy remains strong at higher temperatures.

In another aspect the diamond layer may be brazed to the semiconductorlayer. For aspects including brazing, care must be taken to utilizebrazes that have lower melting temperatures to avoid damage to thesemiconductor and diamond layers. Additionally, the braze should beselected such that metals contained therein will not affect the utilityof the semiconductor layer or the resulting SOD device. A variety ofbrazing alloys may be suitable for use in the present invention. In oneaspect, a braze alloy may include a carbide former such as Ti, Cr, Si,Zr, Mn, and mixtures thereof. Several exemplary braze alloys includethose of Ag—Cu—Ti, Ag—Cu—Sn—Ti, Ni—Cr—B—Si, Ni—Cu—Zr—Ti, Cu—Mn, andmixtures thereof. The brazing alloy may be supplied in any known formsuch as a powder or as a thin foil. Typical brazing temperatures arebelow about 1000° C. such as about 900° C., though many braze materialsmay be selected having lower melting temperatures.

The diamond layers of the present invention may comprise anydiamond-containing material known to one skilled in the art. Generallythe diamond layer can be of any conceivable thickness, depending on theintended function of the diamond layer and the nature of thesemiconductor device. More particularly, in one aspect the diamond layermay have a thickness from about 10 nm to about 2000 μm. In anotheraspect, the diamond layer may have a thickness of from about 10 nm toabout 500 μm. Further, diamond layer thicknesses of less than about 10μm can be suitable for some applications. In yet another aspect, thediamond layer may have a thickness of from about 10 nm to about 100 μm.In a further aspect, the diamond layer may have a thickness of fromabout 10 nm to about 30 μm.

Returning to FIG. 1, the Si substrate 10 and the InN layer 12 may beremoved to expose the semiconductor layer 14. The Si substrate 10 andthe InN layer 12 may be removed by any means known to one of ordinaryskill in the art, including, but not limited to, physical means such asgrinding, sawing, buffing, polishing, sand blasting, etc., and chemicalmeans such as etching, etc. Additionally, either prior to or followingthe removal of the layers, a support substrate 18 may be coupled to thediamond layer 16 to provide added support and/or added functionality tothe SOD device. The support substrate 18 may be of any material known,including Si, W, Ti, Mo, SiC, SiGe, SiB, SiP, epoxies, polyimides,acrylics, etc. The support substrate 18 may be coupled to the diamondlayer 16 using an adhesive, a braze, or any other attachment means. Inone aspect, the support substrate may be applied as a molten alloy. Forexample, in one aspect a molten alloy of SiGe may be applied to thediamond layer and allowed to cool to form the support substrate. Inanother aspect, the molten material forming the support substrate mayinclude boron doped Si to form a p-type semiconductor. In yet anotheraspect, the molten material forming the support substrate may includephosporous doped Si to form a n-type semiconductor.

As shown in FIG. 2, another aspect of the present invention may includedepositing an InN layer 22 onto a lattice-orienting Si substrate 20. TheInN layer 22 may be deposited onto the Si substrate 20 in a mannersimilar to that described in FIG. 1. A layer of GaN 24 may then bedeposited on the InN layer 22, also as described in FIG. 1. A layer ofAlN 26 may then be deposited onto the GaN layer 24. Depositing the AlNlayer 26 onto the GaN 24 layer may include gradually transitioning thelayer of GaN into the layer of AlN. Gradually transitioning the GaNlayer 24 into the AlN layer 26 may include fixing the concentration of Nbeing deposited and varying the deposited concentration of Ga and of Alsuch that a ratio of Ga:Al gradually transitions from about 0:1 to about1:0. Constructing the various layers according to this aspect in such away allows the single crystal nature of the Si substrate 20 to bemaintained throughout the subsequently deposited layers, and thus asingle crystal AlN layer may be formed thereon. A diamond layer 28 maythen be disposed onto the AlN layer 26 as described in FIG. 1. The Sisubstrate 20, InN layer 22, and GaN layer 24 may be removed to exposethe single crystal AlN layer 26. As has been described, surfaceprocessing can be performed to smooth a surface prior to deposition ofany of the recited layers. Additionally, either prior to or followingthe removal of the layers, a support substrate 30 may be coupled to thediamond layer 28 to provide added support and/or added functionality tothe SOD device. The support substrate 30 may be of any material known,including Si, W, Ti, Mo, SiC, SiGe, SiB, SiP, epoxies, polyimides,acrylics, etc. The support substrate 30 may be coupled to the diamondlayer 28 using an adhesive, a braze, or any other attachment means.

SOD device may be utilized to construct a variety of devices, includingLEDs, SAW filters, semiconductor substrates, etc. In one aspect, SODdevices according to various aspects of the present invention may beused to create numerous types of LED devices. Two of the structuraltypes that can be formed by tetrahedral bonding are cubic and hexagonal.Tetrahedral semiconductors tend to be based on cubic structures (Si,SiC, GaAl, GaP . . . etc). Current AlN, GaN, InN for red, blue, greenand white LEDs, however, are based on wurtzite structures. One problemassociated with wurtzite structures concerns the fact that a hexagonalsystem may not be isotropic in electrical and optical transmissions. Inother words, all wurtzitic LEDs are piezoelectric. LED crystals areoften deposited epitaxially, which creates internal stress within thecrystal. This internal stress creates an electric field due to thepiezoelectric nature of the wurtzitic structure. This internalelectrical field will interfere with the externally applied field forlighting the LED. Additionally, light generated in the LED will berefracted due to these internal stresses, and thus will not betransmitted uniformly. Hexagonal structures are particularly problematicin the manufacture of laser diodes. In addition to the problemsdescribed above, hexagonal crystals lack a natural cleavage plane formirror reflection of photons. Current techniques of making laser diodesutilize dry etching techniques to make parallel reflection planes. Dryetching cannot duplicate a natural crystallographic plane, and thus itinevitably leaves pits and curvatures. In contrast, cubic crystals canbe cleaved naturally to form reflection mirrors of high quality, withoutresorting to expensive etching procedures.

Because the energy difference between wurtzite and cubic structures isvery small (for GaN it is about 0.11 eV), it can be overcome with akinetic approach by using a (100) face of the Si substrate. As such,atoms normally deposited as wurtzite deposit as cubic because of theanchoring sites on the (100) face. Thus by using (100) Si substrate, theInN layer, the GaN layer, and the AlN layer can be deposited as a cubic(sphalerite) structure. The resulting cubic nitride LED may exhibitenhanced performance in quantum photon efficiency (i.e. the percentageof power that becomes light) and light extracting efficiency (percentageof light that is emitted), two critical measures for LED performance.Cubic nitride LED materials may be particularly useful for laser diodeLEDs due to the presence of (100) cleavage planes for mirror reflectorsrequired for resonance.

In another aspect, BN can be deposited on the semiconductor layer toform a UV LED. Numerous types of LEDs may be fabricated according toaspects of the present invention, all of which are considered to bewithin the present scope.

Various structural configurations of LEDs are also contemplated. Forexample, two main types of LEDs are commonly used today. One typeincludes the deposition of GaN and other semiconductors on an insulatingsapphire so that both positive and negative electrodes lie on the sameside of the LED. As a result, current must bend around between the twoelectrodes so the entire volume of the doped semiconductor cannot befully utilized. The other type provides an LED having nitridesemiconductors on semiconducting SiC substrate. The SiC can be used asthe electrode in this case, so the LED is symmetrical, allowingelectrical current to pass through essentially all of the semiconductingmaterial. The diamond layer according to various aspects of the presentinvention may be utilized according to this design to produce a moreefficient LED. Though diamond has insulating properties, boron dopingthe diamond layer may make it semiconducting, so that it may be used asan electrode. Alternatively, the conducting metal (e.g. Cu, Ti) can bealternated with diamond and used as an electrode.

Particularly useful structures may also be constructed through furtherdeposition of semiconductor layers. For example, in one aspect a boronnitride (BN) may be deposited onto the layer of AlN. The BN layer may beof any configuration, including, without limitation, cubic BN (cBN),wurtzitic BN (wBN), etc. The BN layer may be deposited directly onto theAlN layer or it may be compositionally graded. Compositional grading maybe accomplished by fixing the concentration of the N being deposited andvarying the deposited concentration of B and of Al such that a ratio ofB:Al gradually transitions from about 0:1 to about 1:0. In other words,the sources of B and Al are varied such that as the Al concentration isdecreased, the B concentration is increased. This gradual transitionfunctions to greatly reduce the lattice mismatch observed whendepositing BN directly on AlN.

The high quality BN layer formed is an ideal seed material fordepositing single crystal CVD diamond. In one aspect, a fast growingnitrogen doped single crystal diamond may be deposited under highermethane conditions, higher pressure, and higher temperature as comparedto conventional CVD processes. A description of such a quick growthprocess can be found in U.S. Pat. No. 6,858,078, filed on Nov. 6, 2002,which is incorporated herein by reference. Diamond layers may also begrown on the BN seed substrate under high-temperature high-pressureconditions. A description of such a process is described in U.S. patentapplication Ser. No. 10/757,715, filed on Jan.13, 2004, U.S. patentapplication Ser. No. 10/775,042, filed on Feb. 6, 2004, and U.S. patentapplication Ser. No. 11/211,139, filed on Aug. 24, 2005, all of whichare incorporated herein by reference.

1. A semiconductor-on-diamond device comprising: a single crystalsemiconductor layer having a lattice substantially oriented by a baselayer upon which the semiconductor layer was previously deposited, saidsemiconductor layer including a member selected from the groupconsisting of InN, AlN, GaN, and combinations thereof; and a layer ofdiamond material coupled to the semiconductor layer.
 2. Thesemiconductor-on-diamond device of claim 1, wherein the single crystalsemiconductor layer is a single crystal layer of AlN.
 3. Thesemiconductor-on-diamond device of claim 2, wherein the single crystallayer of AlN is a layer of cubic AlN.
 4. The semiconductor-on-diamonddevice of claim 1, wherein the single crystal semiconductor layer is asingle crystal layer of GaN.
 5. The semiconductor-on-diamond device ofclaim 4, wherein single crystal layer of GaN is a layer of cubic GaN. 6.The semiconductor-on-diamond device of claim 1, wherein the diamondlayer is located between a support substrate and the single crystalsemiconductor layer.
 7. The semiconductor-on-diamond device of claim 6,wherein the diamond layer is coupled to the support substrate.
 8. Thesemiconductor-on-diamond device of claim 9, wherein the device is anLED.
 9. The semiconductor-on-diamond device of claim 1, wherein thedevice is a semiconductor substrate.
 10. The semiconductor-on-diamonddevice of claim 1, wherein the diamond material layer includes singlecrystalline diamond, polycrystalline diamond, diamond-like carbon, oramorphous diamond.
 11. A method of making a semiconductor-on-diamonddevice, comprising: depositing a base layer onto a lattice-orientingsubstrate such that the base layer lattice is substantially oriented bythe substrate; depositing a semiconductor layer onto the base layer suchthat the semiconductor layer lattice is substantially oriented withrespect to the base layer lattice; disposing a layer of diamond onto thesemiconductor layer; and removing the lattice-orienting substrate andthe base layer from the semiconductor layer.
 12. The method of claim 11,wherein the substrate is of a single crystal orientation.
 13. The methodof claim 12, wherein the substrate is a Si material.
 14. The method ofclaim 11, wherein the semiconductor layer includes GaN, InN, AlN, orcombinations.
 15. The method of claim 14, wherein the semiconductorlayer is GaN.
 16. The method of claim 11, wherein the base layerincludes GaN, InN, AlN, or combinations.
 17. The method of claim 11,wherein depositing the semiconductor layer further comprises: depositinga layer of GaN onto a base layer of InN such that the GaN layer latticeis substantially oriented with respect to the InN layer lattice; anddepositing a layer of AlN onto the layer of GaN such that the AlN layerlattice is substantially oriented with respect to the GaN layer lattice.18. The method of claim 11, wherein depositing the semiconductor layerfurther comprises: depositing a layer of InN onto a base layer of GaNsuch that the InN layer lattice is substantially oriented with respectto the GaN layer lattice; and depositing a layer of AlN onto the layerof InN such that the AlN layer lattice is substantially oriented withrespect to the InN layer lattice.
 19. The method of claim 1, furthercomprising attaching a support substrate to the diamond material layer.20. The method of claim 1, wherein disposing the layer of diamondfurther includes bonding the layer of diamond to the semiconductorlayer.